P r o f e s s i o n a l S k i l l s
Practical Exposures To:
HDL Languages : VHDL, VERILOG, NC- Verilog, System C EDA TOOLS
Simulator : ModelSim 5.7g, Symplicity Orcad, Renoir, Cadence (NC-Sim)
Synthesizer :
Chip verification : Chip Sco Pro
DSP Tools : Matlab 6.5
Other Prog. Languages : Assembly language, C / C++, ,
Embedded Softwares : QNX, SPJ /KEIL Assemblers,
Operating Systems : DOS,Windows 95,98/NT/2000/xp
Target Technology : FPGA Logic, Electronics hardware chips, Mechanical & Electrical
Equipments.
Company : StarVray Co.,Ltd, Daejeon , South korea
Description: This project is related to scanning of digital image for human DNA /RNA for the laboratory test of the dreaded disease like cancer, AIDS, TV etc. In this, individuals DNA scanned image is compared with the samples of tested DNA chip for the dreaded disease and then detection of the disease is being done on the PC screen.
My work for this project is to design and development of Door Logic, Panel control, Temperature monitor controller (max9957) and laser control logic into FPGA.
Client name : Vidar Systems Corporation USA (www.vidar.com )
Project : FPGA Logic Design for PTMA
Target Technology : FPGA Logic, Electronics hardware chips
Company : StarVray Co.,Ltd, Daejeon , South korea
Description: This project is related to FPGA Logic Design and development for the “Prime Trigger Mode Add on” which stores the X-ray energy by Single channel SHA Mode in 16 bit image processor chip AD9826 and offset and control gain amplifiers (AD 8400) and after digitization (AD9826) , this energy is stored into memory and interfaced with PC. For the development of the system design we use AD9826, AD8400, and Phase locked loop (PLL), Low pass filters as main design and digitized data is processed with NIOS II Processor, SDRAM Controllers, and EEPROMS using SOPC Builder of the Altera. This is being communicated through Max232 to the PC.
Client name : Vidar Systems Corporation USA (www.vidar.com )
Project : Dual CIS Camera Board(DCB) Design & Development for Large Format Scanner
Target Technology : FPGA Logic, Electronics hardware chips
Company : StarVray Co.,Ltd, Daejeon , South korea
Description: The project is related to design and development of the SB-42, a 42 inch large format scanner. This scanner uses CIS technology because of its specific advantages over the CCD. It utilizes five fully compatible CSI CA463G Contact Image Sensors (CIS) which are interfaced by three DCB boards (using 3 of the 4 SU connectors on the SUD). Each DCB running concurrently and independently up to two CIS sensor modules using two Wolfson WM8199 image processors (scanner processors). The hardware (FPGA Spartan3) of DCB consists of DCB logic implementation controls along with Image pre-processing algorithms and filtering processes of the input images.
The FPGA logic design of the DCB can be divided into five major parts, namely a. Front End Mux (FIM) b. Segment Descrambler (SED) C. Delay and Tilt compensator, DTC, D. SUD Interface Format, SUDIF and e. DCB-CIS controller.
The FPGA generates clocks for the CISs with exposure-time of 1.56ms in RGB and 0,52ms in grayscale; the video output from the CIS is R, G, or B on two common outputs.
In total 4 analog outputs from two CIS sensors are taken as inputs to the wolfson digitizer. Using the 80MHz (system clock), 16 slices of 80MHz clock from the 5MHz is used as input for Front End Mux. Using Front End MUX (FIM), 4 valid words can be selected from 8 words, each of 16 bits. SED block descrambles all the outputs of FIM. Because of some adjustment pages of pixels are titled, this problem is solved by DTC block by giving some input delays and using compensator to put all pixels in one line. In this way all pixels segments come in one line. SUDIF block simply synchronies output of DTC and interface with CBK logic as well as SUD.
To process the video data, RAM (SDRAM AND SRAM) is needed for Pixel correction coefficient, delay for physical distance between odd and even CIS sensor lines, interpolation/blur filter and the quality feature of averaging multiple exposures . The SDRAM is handled by burst reading, modifying and then burst writing to address segments.Video data is send to the host through the SU-interface witch consists of a registered buffer that connects to the 50 pole flat cable to the SU board.
The data processing in the FPGA is done at speeds higher than the 20 MHz SU clock, thus an external PLL is used to multiply to a 80MHz frequency. The pixel data is sent over the SU-interface at a 20MHz data rate 12bit pr. Pixel.
Client name : Contex Corporation USA (www.contex.com )
Target Technology : VLSI & SOFTWARES(Matrox Meteor-II & ARM Emulator)
Company : IT Magic Co.Ltd , Seoul
Description: This project is related to digital image stabilization with sub-image novel phase correlation based global motion estimation and maximum peak filtering based motion correction. Global motion is estimated from the local motion of four sub-images each of which is detected using phase correlation (PC) based motion estimation. The correlation surface using Phase correlation techniques determine local motion vector (LMV) and most peak amplitude from block of LMV decides its global motion vector (GMV), thereby Accumulating motion vector (AMV) for panning. The proposed algorithm can make a robust digital image stabilization when camera affected by vibration or unwanted movement.
The Design algorithms have been implemented and verified with Frame grabber board ( Matrox Meteor-II Mil-lite software) that is interfaced with camcorder and PC. Similarly, The same design has also been tested by us in the ARM Emulator and ported into DM320 Board (ARM9TDMI core, DSP core).
My role: algorithm development and leading the team from the Present Employer and collaborate with the team of University Researchers.
Project Partner : Image Processing and Intelligent Systems Laboratory Image Engineering, Graduate School of Advanced Imaging Science, Multimedia, and Film, Chung-Ang University , Seoul. We developed PCM based stabilization algorithm in association with university sent two international papers for the journal:
Paper accepted :
GSPX 2005 (www.gspx.com ) ON VLSI Architecture design of Real time image stabilization
Electronic Journal : Technical Acoustics: http://ejta.org/en/bibhuti1
Client : Samsung Electronics Ltd, Seoul
Project : H.264/AVC IP core Development
Target Technology : Virtex-4(FPGA) VLSI & SOFTWARES.
Company : ITMagic Co.Ltd , Seoul
Description: This project is related to VLSI (VIRTEX 4 FPGA) implementation of H.264 which is used for the compression and decompression of real time video and their processing .The input image (CIF) is divided into frames of 16x16 pixels called as micro blocks and each micro block is encoded in intra (I frame) and (P) frame mode. For the first I frame, default pixel values are taken as reference for the motion estimation and similarly for the next frame, previous frame output will take as a reference for their motion estimation. Therefore, prediction microblock,P is formed on the basis of reconstructed frame. The residual or difference block is transform by performing DCT on it and then quantized by a given set of pixel values, known as scalar quantization to get set of quantized transform Coefficients. These transform coefficients are reordered (like Zigzag Scan) and then Entropy coding is used to get compressed image bit stream and this is passed to the Network
Abstraction Layer (NAL) for transmission or storage. For the entropy coding, CAVLC is used. The inverse procedures are used for the reconstruction of the encoded quantized image. In this the Quantized micro block coefficients are re-scaled (Inverse quantization) and inverse Transformed (IDCT) to produce difference micro block (Dn) and analyzed the distorted micro blocks from the previous block because after quantization, some part of bit frame may be lost.
My Role: Hardware Design, RTL Coding, functional verification and Synthesis
Of the Two Major Blocks: CAVLC Decoder and Deblocking Filter
Client : Samsung Electronics Ltd, Seoul
Project : Correlation surface determination
Target Technology : VLSI & SOFTWARES.
Company : ITMagic Co.Ltd , Seoul
Description: This project is related to VLSI implementation of Sandy Tukey Butterfly Architecture and IP core development of 64 Point FFT (Radix 8) into Spartan 3 FPGA. This is further used for the Correlation surface determination for the Real time image Stabilization.
My Role: Hardware Design, RTL Coding, functional verification and Synthesis
Project : Motion Estimation in MPEG-4
Target Technology : VLSI (FPGA) Implementation
Company : DCA InfoTech,Pune( India)
Description: This Project is related to VLSI Design and development of the Motion Estimation (SAD Architecture) in MPEG-4 for comparing the pixel position and calculating its MAD for exact position for Real time image.
My Role : Team Leading, Hardware Design, RTL Coding, functional verification and Synthesis
Project: Encryption and Decryption for Biometric Finger print Sensor (Triple AES Core Development )
Target Technology : VLSI (SPARTAN2 100 FG 456)
Company : DCA InfoTech, Pune( India)
Description: This Project is related to VLSI design & development of encryption and decryption logic for the finger print image using AES algorithms. Using This Algorithm 128 bit for the key is used to maintain the secrecy.
My Role: Team Leading, Hardware Design, functional verification
Project : Customized Design Of Music Simulator
Company : DCA InfoTech, Pune ( India)
Description: This project is related to design and development of Midi file super imposer and the product that will help us develop a stand- alone FDC using VLSI technology and interface it with the FDD.The MIDI file super imposer and the FDC are embedded in an IC called “Customized Design Of Music Simulator”.
My Role: Team Leading, Hardware Design functional verification.
Company : DCA InfoTech,Pune( India)
Description: This Project is related to multiplication of two floating point numbers in VLSI (SPARTAN2) technology. In this project, redundant logic has been used for speed and area trade off.
Client : Sangamner College, Sangamner ( Nasik)
My Role : Team Leading, Hardware Design, functional verification and Synthesis
Project : Hard Disc Based MP3 Player.
Company : DCA InfoTech,Pune( India)
Description: This product is related to the development of hard disc MP3 player in which Thousands of songs can be stored, played using very few no. of keys to drive. This project will be used in the BUSES, CARS whenever they are in long drive.
My Role: Team Leading, Hardware Design, functional verification and Synthesis
Project : VLSI Implementation Of JPEG CODEC for B/W Camera
Target Technology : VLSI & SOFTWARES.
Company : Info Dynamics Integration Technologies ,Pune( India)
Description: This project is related to digital image coding & compression into FPGA by performing Discrete cosine Transform(DCT) on input images ,quantization and zigzag scanning and test its affectivity by performing inverse DCT and inverse procedure to get original images. The given input images are converted into FPGA readable input files using C program and are stored into memory. Similarly FPGA generated out files are converted to PGM images by another C program. These FPGA perform all the DCT & IDCT fetching data from existing memory with these devices.
My Role: Team Leading, Hardware Design, RTL Coding, functional verification and Synthesis
Client : Fulcrum Logic. Inc, Pune
Company : Info Dynamics Integration Technologies, Pune ( India)
Description: This project is related to analysis –Synthesis of speech signal First the speech Signal ,after getting output from ADC, segment the voice into 16 channel to Analyse its spectrum simultaneously voiced and unvoiced condition of speech is Checked followed by pitch detection in the analyser part of the project . In the synthesizer part of the project, again centre frequency (output of analyser) is Segmented and Band pass filtered and the output of the random no. generator/pulse generator goes to each output of the BPF and then all output is summed.
Client : IDIT, Pune
My Role: Team Leading, Hardware Design, functional verification and Synthesis
Project : Radix 2(8 Point) “Fast Fourier Transform”
Company : Info Dynamics Integration Technologies, Pune ( India)
Description: This project is related to VLSI design and implementation of Radix 2(8 point) Fast Fourier Transform as part of Trainee design Engineer” in the company.
My Role: Hardware design, RTL Coding, functional verification and Synthesis
Project : Design of “8051 A Micro controller”
Company : Info Dynamics Integration Technologies, Pune ( India)
Description: This project is related to VLSI design and implement of the functionalities of
8051 with few Bit and Byte level of Instructions. & implemented with the internal memory
(ROM and RAM) and two ports.
My Role: RTL Coding, functional verification and Synthesis